We are at the dawn of a new era. New emerging applications will revolutionize the way we communicate, share ideas, work, travel, play, watch sports, and enjoy movies; in a single word, the way we live. For Internet of Things (IoT) applications, it is estimated that up to hundred devices will be connected and share information for each person, from wearable devices -(such as smartwatches) to disposable lab-on-a-chip (for smart health care). Those devices will generate an enormous amount of data, posing unprecedented challenges on each element of the network. For automotive applications, advanced driver assistance systems (ADAS) are expected to evolve in self-driving cars with automatic parking and predictive-collision-avoidance features. For mobile applications, virtual reality (VR) games and videos are expected in the near future.
Fifth generation mobile networks (5G) is the wireless standard that will address these challenges. 100× higher data rate is needed at 100× higher network efficiency. For the network to provide high-quality services such as 3D 360° video and 360° surround solutions to enable virtual reality (VR) while being transparent to the user, better than 1 ms latency is needed. This is the first time that a wireless standard puts such stringent specifications to improve the user experience. To send so much data in such a limited time, an enormous amount of bandwidth is required. The spectrum in the low GHz range is already overcrowded; therefore, mm-Wave wireless communication is going to happen in the near future.
CMOS is the technology of choice for mass production digital circuits. It guarantees high yield and low costs, while the aggressive scaling of the minimum feature size allows to integrate low power mm-Wave analog building blocks together with the baseband digital signal processing. CMOS is therefore a key technology for the success of 5G mm-Wave front-ends and has attracted a growing attention in the last decade from both industries and research institutes.
However, aggressive technology scaling does not provide only benefits. The low-level metal interconnections get thinner and closer to the substrate, seriously limiting the achievable fMAX of active devices and the maximum quality factor of on-chip passive devices. The supply voltage scales as well, making the classical analog design trade-offs tighter. Moreover, the requirements on large bandwidth of operation should be met under process, voltage, and temperature (PVT) variations, and extra margin should be taken to allow substantial model inaccuracy due to the high frequency of operation.
This work focuses on these challenges and proposes design techniques for several building blocks that currently limit the performance of mm-Wave transceivers. The distinctive features of high-speed analog design in deep-scaled CMOS will be addressed, and a comparison with older technology node will be provided. Transformer-based low loss broadband filters that realize interstage matching, power division/combining, and impedance transformation will be discussed in great detail. Simple design equations that shed new insights on these pervasive kinds of filters will be provided. Second-order effects due to physical layout implementation will be addressed and simple solutions will be proposed. Tuning extension techniques for integrated mm-Wave oscillators will be discussed. The design, layout, and measurements details of five state-of-the-art building blocks that leverage the proposed design techniques will be presented. (1) An E-Band quadrature voltage controlled oscillator tunable over two bands of almost 5 GHz each separated in frequency, while achieving state-of-the-art phase noise and power consumption is demonstrated. The integrated prototype realizes accurate quadrature phases and occupies only 0.031 mm2. (2) A wideband inductor-less frequency divide-by-4 that allows low power operation with wide margin over the whole E-Band (60−90 GHz) and beyond is reported for the first time. (3) A broadband low-noise amplifier for E-Band point-to-point communication links that achieves a figure of merit ≈10.5 dB better than the state-of-the-art designs in the same band is shown. (4) The LNA is further integrated into a broadband sliding-IF receiver that demonstrates 30.8 dB conversion gain with ¡1 dB in-band ripple over a 27.5 GHz BW−3dB while achieving a 7.3 dB minimum NF with less than 2 dB variation from 61.4 to 88.9 GHz. This wideband state-of-the-art performance enables robust and low power multi-Gb/s wireless communication over short to medium distance over the complete E-Band with wide margin. (5) A 29–57 GHz (65% BW) AM-PM compensated class-AB power amplifier tailored for 5G phased arrays is demonstrated. This integrated prototype shows outstanding AM-PM linearity allowing excellent EVM and ACPR while amplifying wideband modulated signals with high PAPR. All designs were implemented in a 28-nm CMOS technology without RF ultra-thick top metal option.
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